Senior Engineer – Physical Design (ASIC/SoC Place & Route)

About this role

TSMC is seeking a Senior Engineer – Physical Design (ASIC/SoC Place & Route) to join their Silicon & Chip Design team. This role involves cutting-edge work in AI acceleration and semiconductor technologies. The ideal candidate will have deep expertise in their area of specialization and a passion for pushing the boundaries of hardware and software co-design.

What you’ll do

• Define micro-architecture and implement RTL for high-performance blocks
• Partner with verification, DFT and physical design to close timing, power and area
• Drive designs from specification through tape-out and post-silicon bring-up

Required silicon / compute stack

• SystemVerilog
• RTL
• UVM
• Synthesis / STA
• DFT
• Physical Design

Requirements

• BS/MS in Electrical or Computer Engineering (or equivalent experience)
• Strong SystemVerilog/Verilog and industry-standard EDA tool experience
• Solid understanding of digital design, timing closure and low-power techniques

Typical for this role category. See the employer’s official posting for the exact requirements.

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, manufacturing leading-edge process nodes and advanced packaging for virtually every major AI chip company.